1. Field of the Invention
The present invention relates generally to the fabrication of semiconductor integrated circuit devices, and more specifically to a technique for fabricating contacts with zero offset.
2. Description of the Prior Art
Formation of field effect transistors in integrated circuits often includes the formation of lightly doped drain (LDD) regions adjacent the channel. This minimizes hot-electron effects, and improves operation of the transistor. In order to form these LDD regions using a self-aligned process, a sidewall oxide (SiO.sub.2) spacer is formed along side the transistor gate.
When forming the oxide sidewall spacers, it is necessary to over etch the oxide layer from which they are formed in order to insure that all contact areas are completely clear. This over etching also damages field oxide regions, and significant over etch of the field oxide regions can allow implanted dopants to penetrate through the field oxide during later source/drain formation.
Also, it is necessary to insure that substrate contacts are not misaligned so as to extend over the gate electrodes. When this type of misalignment happens, etching required to clear the contact of interlevel oxide can damage the oxide cap and sidewall spacers on the gate. Significant damage of the oxide sidewall spacer can cause a short between the sidewall and gate.
A number of processing approaches have been used to address these and other problems. One approach is to deposit a thick oxide on top of the gate prior to the gate definition etch. This provides some margin, but does not solve the problem of the required enclosure near gate electrodes.
Other approaches use additional poly layers as "landing pads" for contacts in the matrix of DRAM and SRAM devices.
As described in parent application Ser. No. 639,316, which has been incorporated herein to by reference, spacers formed of silicon nitride may be used for LDD definition. These spacers protect the gate from later over etching during contact formation, because silicon nitride and oxide can be highly selectively etched over each other.
As device geometries continue to shrink, contacts are formed which have a very high aspect ratio. This is particularly true between adjacent gate electrodes in a device having regular structure, such as a memory matrix. It is difficult to provide sufficient barrier metal at the bottom of these high aspect ratio openings to provide proper protection for the underlying substrate.
It would therefore be desirable to provide an improved technique for fabricating contacts and semiconductor integrated circuits which addresses and solves the problems described above.